About the position
Responsibilities
• Design a hardware-friendly algorithm for compressing activations, weights and instructions in an ML accelerator
• Develop a proof-of-concept hardware implementation of the compressor-decompressor
• Study trade-offs between hardware complexity, performance, compression loss
• Collaborate with ML model owners to estimate impact of compression on model quality
Requirements
• Enrolled in a Masters program in Electrical Engineering, Computer Engineering or equivalent
• Strong understanding of computer architecture for domain-specific accelerators
• Strong programming skills in C++ and/or Python
• Proficiency in digital design using High-level synthesis, SystemVerilog or similar languages
Nice-to-haves
• Enrolled in a PhD program in Electrical Engineering, Computer Engineering or equivalent
• Understanding of ML numerics, error analysis and model quality evaluations
• Experience with domain-specific languages for hardware design (Eg. Chisel, Magma etc.)
• Familiarity with high-level architectural simulators such as Gem5
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